ARM ARM1176JZF-S - Table 3-123 Monitor Vector Base Address Register Bit Functions; Table 3-124 Results of Access to the Monitor Vector Base Address Register

System Control Coprocessor
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Table 3-123 lists how the bit values correspond with the Monitor Vector Base Address Register
functions.
When an exception branches to the Secure Monitor mode, the core branches to address:
Monitor_Base_Address + Exception_Vector_Address.
The Secure Monitor Call Exception caused by an SMC instruction branches to Secure Monitor
mode. You can configure IRQ, FIQ, and External abort exceptions to branch to Secure Monitor
mode, see c1, Secure Configuration Register on page 3-52. These are the only exceptions that
can branch to Secure Monitor mode and that use the Monitor Vector Base Address Register to
calculate the branch address. For more information about exceptions, see Exception vectors on
page 2-48.
Note
The Monitor Vector Base Address Register is 0x00000000 at reset. The Secure boot code must
program the register with an appropriate value for the Secure Monitor.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Table 3-124 lists the results of attempted access for each mode.
To use the Monitor Vector Base Address Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c12
• CRm set to c0
• Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c12, c0, 1 ; Read Monitor Vector Base Address Register
MCR p15, 0, <Rd>, c12, c0, 1 ; Write Monitor Vector Base Address Register
3.2.45 c12, Interrupt Status Register
The purpose of the Interrupt Status Register is to:
• reflect the state of the nFIQ and nIRQ pins on the processor
• to reflect the state of external aborts.
Table 3-123 Monitor Vector Base Address Register bit functions
Bits Field name Function
[31:5] Monitor vector base
address
Determines the location that the core branches to on a Secure Monitor mode exception.
Holds the base address. The reset value is 0.
[4:0] SBZ UNP/SBZ.
Table 3-124 Results of access to the Monitor Vector Base Address Register
Secure Privileged
Non-secure Privileged User
Read Write
Data Data Undefined exception Undefined exception