Trace Interface Port
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 15-8
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In Figure 15-1 on page 15-7, the CP bit is 0 for CP14 or 1 for CP15.
Non-ETM instructions are not presented on this interface.
In contrast to the debug logic, the core makes no attempt to decode if a given ETM register exists
or not. If a register does not exist, the write is silently ignored. For more details see the
Embedded Trace Macrocell Architecture Specification.
15.1.7 Other connections to the core
The signals that Table 15-11 lists are also connected to the core.
Table 15-11 Other connections
Signal name Direction Description
EVNTBUS[19:0] Output Gives the status of the performance monitoring events. See c15, Performance
Monitor Control Register on page 3-133.
ETMEXTOUT[1:0] Input Provides feedback to the core of the EVNTBUS signals after being passed through
ETM triggering facilities and comparators. This enables the performance
monitoring facilities provide by the processor to be conditioned in the same way as
ETM events. For more details see c15, Performance Monitor Control Register on
page 3-133 and the CoreSight ETM11 Technical Reference Manual.
ETMPWRUP Input Indicates that the ETM is active. When LOW the Trace Interface must be clock
gated to conserve power.
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