Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-3
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1.2 Extensions to ARMv6
The ARM1176JZF-S processor provides support for extensions to ARMv6 that include:
• Store and Load Exclusive instructions for bytes, halfwords and doublewords and a new
Clear Exclusive instruction.
• A true no-operation instruction and yield instruction.
• Architectural remap registers.
• Cache size restriction through CP15 c1. You can restrict cache size to 16KB for Operating
Systems (OSs) that do not support page coloring.
• Revised use of TEX remap bits. The ARMv6 MMU page table descriptors use a large
number of bits to describe all of the options for inner and outer cachability. In reality, it is
believed that no application requires all of these options simultaneously. Therefore, it is
possible to configure the ARM1176JZF-S processor to support only a small number of
options by means of the TEX remap mechanism. This implies a level of indirection in the
page table mappings.
The TEX CB encoding table provides two OS managed page table bits. For binary
compatibility with existing ARMv6 ports of OSs, this gives a separate mode of operation
of the MMU. This is called the TEX Remap configuration and is controlled by bit [28] TR
in CP15 Register 1.
• Revised use of AP bits. In the ARM1176JZF-S processor the APX and AP[1:0] encoding
b111 is Privileged or User mode read only access. AP[0] indicates an abort type, Access
Bit fault, when CP15 c1[29] is 1.
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