Coprocessor Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-2
ID012310 Non-Confidential, Unrestricted Access
11.1 About the coprocessor interface
The processor supports the connection of on-chip coprocessors through an external coprocessor
interface. All types of coprocessor instruction are supported.
The ARM instruction set supports the connection of 16 coprocessors, numbered 0-15, to an
ARM processor. In the processor, the following coprocessor numbers are reserved:
CP10 VFP control
CP11 VFP control
CP14 Debug and ETM control
CP15 System control.
You can use CP0-9, CP12, and CP13 for your own external coprocessors.
The processor is designed to pass instructions to several coprocessors and exchange data with
them. These coprocessors are intended to run in step with the core and are pipelined in a similar
way to the core. Instructions are passed out of the Fetch stage of the core pipeline to the
coprocessor and decoded. The decoded instruction is passed down its own pipeline. Coprocessor
instructions can be canceled by the core if a condition code fails, or the entire coprocessor
pipeline can be flushed in the event of a mispredicted branch. Load and store data are also
required to pass between the core Logic Store Unit (LSU) and the coprocessor pipeline.
The coprocessor interface operates over a two-cycle delay. Any signal passing from the core to
the coprocessor, or from the coprocessor to the core, is given a whole clock cycle to propagate
from one to the other. This means that a signal crossing the interface is clocked out of a register
on one side of the interface and clocked directly into another register on the other side. No
combinatorial process must intervene. This constraint exists because the core and coprocessor
can be placed a considerable distance apart and generous timing margins are necessary to cover
signal propagation times. This delay in signal propagation makes it difficult to maintain pipeline
synchronization, ruling out a tightly-coupled synchronization method.
The processor implements a token-based pipeline synchronization method that enables some
slack between the two pipelines, while ensuring that the pipelines are correctly aligned for
crucial transfers of information.
To Next Page
Loading...
Need help?
General
