ARM ARM1176JZF-S - Figure 20-2 FMRRD Instruction Format

VFP Programmer’s Model
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Notes
Conversions In the programmer’s model, FMDRR does not perform any conversion of the
value transferred. Arithmetic instructions using either Rd or Rn treat the value as
an integer, whereas most VFP instructions treat the Dm value as a
double-precision floating-point number.
20.3.2 FMRRD
FMRRD transfers data in a VFP11 double-precision register to two ARM11 registers. The
ARM11 registers do not have to be contiguous. Figure 20-2 shows the format of the FMRRD
instruction.
Figure 20-2 FMRRD instruction format
Syntax
FMRRD {<cond>} <Rd>, <Rn>, <Dm>
where:
<cond> Is the condition under which the instruction is executed. If <cond> is omitted, the
AL, always, condition is used.
<Rd> Specifies the destination ARM11 register for the lower 32 bits of the operand.
<Rn> Specifies the destination ARM11 register for the upper 32 bits of the operand.
<Dm> Specifies the source double-precision VFP11 coprocessor register.
Architecture version
D variants only
Exceptions
None
Operation
if ConditionPassed(cond) then
Rn = Dm[upper half]
Rd = Dm[lower half]
Notes
Use of R15 If R15 is specified for
<Rd> or <Rn> , the results are Unpredictable.
Conversions In the programmer’s model, FMRRD does not perform any conversion of the
value transferred. Arithmetic instructions using Rd and Rn treat the contents as an
integer, whereas most VFP instructions treat the Dm value as a double-precision
floating-point number.
1 1 0 0 0 1 0 1 Rn Rd 1 0 1 1 0 0 0 1 Dm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond