ARM ARM1176JZF-S User Manual

Memory Management Unit
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-48
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If the second level descriptor describes a large page, a small page, or an extended small page
when the Force AP bit is set and the MMU is in ARMv6 mode, Access bit faults might be
generated if AP[0]=0.
Second-level large page base address
If bits [1:0] of the second-level descriptor are b01, then a large page table walk is required.
Figure 6-14 shows the translation process for a 64KB large page using ARMv6 format, AP bits
disabled.
Figure 6-14 Large page table walk, ARMv6 format
Figure 6-15 on page 6-49 shows the translation process for a 64KB large page, or a 16KB large
page subpage, using backwards-compatible format, AP bits enabled.
N
S
X
N
STEX
1
Coarse page table base address
31 1098 54 210
P Domain 0
First-level table index
31 20 19 12 11 0
Page index
Translation base
31 14 13 0
1
Page base address
31 12111098 6543210
n
G
A
P
X
SBZ
AP C B 0
0
Coarse page table base address
31 10 9 2 1 0
Second-level
table index
0
0
Translation base
31 14 13 0
First-level table index 0
21
Page index
Page base address
31 0
Second-level descriptor address
Second-level descriptor
Physical address
First-level descriptor
First-level descriptor address
Modified virtual address
Translation table base
16 15
16 15
16 15
14
Second-level
table index
3
SBZ SBZ

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English