System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-42
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For example:
MRC p15, 0, <Rd>, c0, c2, 3 ;Read Instruction Set Attributes Register 3
c0, Instruction Set Attributes Register 4
The purpose of the Instruction Set Attributes Register 4 is to provide information about the
instruction set that the processor supports beyond the basic set.
The Instruction Set Attributes Register 4 is:
•in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-25 shows the bit arrangement for Instruction Set Attributes Register 4.
Figure 3-25 Instruction Set Attributes Register 4 format
Table 3-36 lists how the bit values correspond with the Instruction Set Attributes Register 4
functions.
Reserved - - - - - -Reserved
31 16 15 12 11 8 7 4 3 0
20 1928 27 24 23
Table 3-36 Instruction Set Attributes Register 4 bit functions
Bits Field name Function
[31:28] - Reserved. RAZ.
[27:24] - Reserved. RAZ.
[23:20] - Indicates fractional support for synchronization primitive instructions.
0x0
, ARM1176JZF-S processors support all synchronization primitive instructions.
See Table 3-34 on page 3-41.
[19:16] - Indicates support for barrier instructions.
0x0
, None. ARM1176JZF-S processors support only the CP15 barrier operations.
[15:12] - Indicates support for SMC instructions.
0x1
, ARM1176JZF-S processors support SMC.
[11:8] - Indicates support for writeback instructions.
0x1
, ARM1176JZF-S processors support all defined writeback addressing modes.
[7:4] - Indicates support for with shift instructions.
0x4
, ARM1176JZF-S processors support:
• shifts of loads and stores over the range LSL 0-3
• constant shift options
• register controlled shift options.
[3:0] - Indicates support for Unprivileged instructions.
0x1
, ARM1176JZF-S processors support LDRBT, LDRT, STRBT, and STRT.
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