System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-139
ID012310 Non-Confidential, Unrestricted Access
Access to the Count Register 0 in User mode depends on the V bit, see c15, Secure User and
Non-secure Access Validation Control Register on page 3-132. The Count Register 0 is always
accessible in Privileged modes. Table 3-140 lists the results of attempted access for each mode.
To access Count Register 1 read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c15
• CRm set to c12
• Opcode_2 set to 2.
For Example:
MRC p15, 0, <Rd>, c15, c12, 2 ; Read Count Register 0
MCR p15, 0, <Rd>, c15, c12, 2 ; Write Count Register 0
The value in Count Register 0 is 0 at Reset.
You can use the Performance Monitor Control Register to set Count Register 0 to zero.
3.2.54 c15, Count Register 1
The purpose of the Count Register 1 is to count instances of an event that the Performance
Monitor Control Register selects.
The Count Register 1:
•is in CP15 c15
• is a 32-bit read/write register common to Secure and Non-secure worlds
• counts up and can trigger an interrupt on overflow.
Count Register 1 bits [31:0] contain the count value. The reset value is 0.
You can use this register in conjunction with the Performance Monitor Control Register, the
Cycle Count Register, and Count Register 0 to provide a variety of useful metrics that enable
you to optimize system performance.
Note
• In Debug state the counter is disabled.
• When the core is in a mode where non-invasive debug is not permitted, set by SPNIDEN
and the SUNIDEN bit, see c1, Secure Debug Enable Register on page 3-54, the processor
does not count events.
Table 3-140 Results of access to the Count Register 0
V bit
Secure Privileged Non-secure Privileged User
Read Write Read Write Read Write
0 Data Data Data Data Undefined exception Undefined exception
1 Data Data Data Data Data Data
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