ARM ARM1176JZF-S - Table 8-41 Noncacheable LDM15; Table 8-42 Noncacheable LDM16

Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-25
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8.5.18 Noncacheable LDM15
A Noncacheable LDM15 is split into two or three operations as shown in Table 8-41.
8.5.19 Noncacheable LDM16
A Noncacheable LDM16 is split into two or three operations as shown in Table 8-41.
0x10 , word 4 LDM4 from 0x10 + LDM8 from 0x00 + LDM2 from 0x00
0x14
, word 5 LDM3 from 0x14 + LDM8 from 0x00 + LDM3 from 0x00
0x18
, word 6 LDM2 from 0x18 + LDM8 from 0x00 + LDM4 from 0x00
0x1C
, word 7 LDR from 0x1C + LDM8 from 0x00 + LDM5 from 0x00
Table 8-40 Noncacheable LDM14 (continued)
Address[4:0] Operations
Table 8-41 Noncacheable LDM15
Address[4:0] Operations
0x00 , word 0 LDM8 from 0x00 + LDM7 from 0x00
0x04
, word 1 LDM7 from 0x04 + LDM8 from 0x00
0x08
, word 2 LDM6 from 0x08 + LDM8 from 0x00 + LDR from 0x00
0x0C
, word 3 LDM5 from 0x0C + LDM8 from 0x00 + LDM2 from 0x00
0x10
, word 4 LDM4 from 0x10 + LDM8 from 0x00 + LDM3 from 0x00
0x14
, word 5 LDM3 from 0x14 + LDM8 from 0x00 + LDM4 from 0x00
0x18
, word 6 LDM2 from 0x18 + LDM8 from 0x00 + LDM5 from 0x00
0x1C
, word 7 LDR from 0x1C + LDM8 from 0x00 + LDM6 from 0x00
Table 8-42 Noncacheable LDM16
Address[4:0] Operations
0x00 , word 0 LDM8 from 0x00 + LDM8 from 0x00
0x04
, word 1 LDM7 from 0x04 + LDM8 from 0x00 + LDR from 0x00
0x08
, word 2 LDM6 from 0x08 + LDM8 from 0x00 + LDM2 from 0x00
0x0C
, word 3 LDM5 from 0x0C + LDM8 from 0x00 + LDM3 from 0x00
0x10
, word 4 LDM4 from 0x10 + LDM8 from 0x00 + LDM4 from 0x00
0x14
, word 5 LDM3 from 0x14 + LDM8 from 0x00 + LDM5 from 0x00
0x18
, word 6 LDM2 from 0x18 + LDM8 from 0x00 + LDM6 from 0x00
0x1C
, word 7 LDR from 0x1C + LDM8 from 0x00 + LDM7 from 0x00