System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-122
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You can configure IRQ, FIQ, and External abort exceptions to branch to Secure Monitor mode,
see c1, Secure Configuration Register on page 3-52. In this case the processor uses the Monitor
Vector Base Address, see c12, Monitor Vector Base Address Register, to calculate the branch
address. The Reset exception always branches to
0x00000000
, regardless of the value of the
Vector Base Address except when the processor uses high vectors.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Table 3-122 lists the results of attempted access for each mode.
To use the Secure or Non-secure Vector Base Address Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c12
• CRm set to c0
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c12, c0, 0 ; Read Secure or Non-secure Vector Base Address Register
MCR p15, 0, <Rd>, c12, c0, 0 ; Write Secure or Non-secure Vector Base Address Register
3.2.44 c12, Monitor Vector Base Address Register
The purpose of the Monitor Vector Base Address Register is to hold the base address for the
Secure Monitor exception vector. For more information, see Exceptions on page 2-36.
The Monitor Vector Base Address Register is:
• in CP15 c12
• a 32-bit read/write register in the Secure world only
• accessible in Secure privileged modes only.
Figure 3-66 shows the arrangement of bits in the register.
Figure 3-66 Monitor Vector Base Address Register format
Table 3-122 Results of access to the Secure or Non-secure Vector Base Address Register
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Secure data Secure data Non-secure data Non-secure data Undefined exception
Monitor vector base address
31 54 0
SBZ
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