System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-66
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Table 3-62 lists the results of attempted access for each mode.
Note
When the SCR EA bit is set, see c1, Secure Configuration Register on page 3-52, the processor
writes to the Secure Data Fault Status Register on a Secure Monitor entry caused by an external
abort.
To use the Data Fault Status Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c5
• CRm set to c0
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c5, c0, 0 ; Read Data Fault Status Register
MCR p15, 0, <Rd>, c5, c0, 0 ; Write Data Fault Status Register
3.2.18 c5, Instruction Fault Status Register
The purpose of the Instruction Fault Status Register (IFSR) is to hold the source of the last
instruction fault.
Table 3-63 on page 3-67 lists the purposes of the individual bits in IFSR.
The Instruction Fault Status Register is:
•in CP15 c5
• a 32-bit read/write register banked for Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-37 shows the bit arrangement of the Instruction Fault Status Register.
Figure 3-37 Instruction Fault Status Register format
Table 3-62 Results of access to the Data Fault Status Register
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Secure data Secure data Non-secure data Non-secure data Undefined exception
0
S
B
Z
S
D
UNP/SBZ
31 30
StatusUNP/SBZ
4
910111213
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