ARM ARM1176JZF-S - Table 8-32 Noncacheable LDM7 from Word 2, 3, 4, 5, 6, or 7; Noncacheable LDM8 from Word 1, 2, 3, 4, 5, 6, or 7; Table 8-35 Noncacheable LDM9

Level Two Interface
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8.5.11 Noncacheable LDM8
Table 8-33 shows the values of ARADDRRW, ARBURSTRW, ARSIZERW, and
ARLENRW for a Noncacheable LDM8 addressing word 0.
A Noncacheable LDM8 addressing words 1 to 7 is split into two operations as shown in
Table 8-34.
8.5.12 Noncacheable LDM9
A Noncacheable LDM9 is split into two operations as shown in Table 8-35.
0x14 , word 5 LDM3 from 0x14 + LDM4 from 0x00
0x18
, word 6 LDM2 from 0x18 + LDM5 from 0x00
0x1C
, word 7 LDR from 0x1C + LDM6 from 0x00
Table 8-32 Noncacheable LDM7 from word 2, 3, 4, 5, 6, or 7 (continued)
Address[4:0] Operations
Table 8-33 Noncacheable LDM8 from word 0
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 64-bit 4 data transfers
Table 8-34 Noncacheable LDM8 from word 1, 2, 3, 4, 5, 6, or 7
Address[4:0] Operations
0x04 , word 1 LDM7 from 0x04 + LDR from 0x00
0x08
, word 2 LDM6 from 0x08 + LDM2 from 0x00
0x0C
, word 3 LDM5 from 0x0C + LDM3 from 0x00
0x10
, word 4 LDM4 from 0x10 + LDM4 from 0x00
0x14
, word 5 LDM3 from 0x14 + LDM5 from 0x00
0x18
, word 6 LDM2 from 0x18 + LDM6 from 0x00
0x1C
, word 7 LDR from 0x1C + LDM7 from 0x00
Table 8-35 Noncacheable LDM9
Address[4:0] Operations
0x00 , word 0 LDM8 from 0x00 + LDR from 0x00
0x04
, word 1 LDM7 from 0x04 + LDM2 from 0x00
0x08
, word 2 LDM6 from 0x08 + LDM3 from 0x00
0x0C
, word 3 LDM5 from 0x0C + LDM4 from 0x00
0x10
, word 4 LDM4 from 0x10 + LDM5 from 0x00