Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-26
ID012310 Non-Confidential, Unrestricted Access
1.8 Pipeline stages
Figure 1-2 shows:
• the two Fetch stages
• a Decode stage
• an Issue stage
• the four stages of the ARM1176JZF-S integer execution pipeline.
These eight stages make up the processor pipeline.
Figure 1-2 ARM1176JZF-S pipeline stages
From Figure 1-2, the pipeline operations are:
Fe1 First stage of instruction fetch where address is issued to memory and data returns
from memory
Fe2 Second stage of instruction fetch and branch prediction.
De Instruction decode.
Iss Register read and instruction issue.
Sh Shifter stage.
ALU Main integer operation calculation.
Sat Pipeline stage to enable saturation of integer results.
WBex Write back of data from the multiply or main execution pipelines.
MAC1 First stage of the multiply-accumulate pipeline.
MAC2 Second stage of the multiply-accumulate pipeline.
MAC3 Third stage of the multiply-accumulate pipeline.
ADD Address generation stage.
DC1 First stage of data cache access.
DC2 Second stage of data cache access.
WBls Write back of data from the Load Store Unit.
By overlapping the various stages of operation, the ARM1176JZF-S processor maximizes the
clock rate achievable to execute each instruction. It delivers a throughput approaching one
instruction for each cycle.
1st fetch
stage
2nd fetch
stage
Instruction
decode
Reg. read
and issue
Shifter
stage
ALU
operation
Saturation
stage
Writeback
Mul/ALU
Fe1 Fe2 De Iss Sh ALU Sat WBex
1st multiply
acc. stage
2nd multiply
acc. stage
MAC1 MAC2 MAC3
Address
generation
Data
cache 1
Data
cache 2
Writeback
from LSU
ADD DC1 DC2 WBls
3rd multiply
acc. stage
To Next Page
Loading...
Need help?
General
