Trace Interface Port
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 15-5
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Table 15-5 lists the ETMDACTL[17:0] signals.
15.1.4 Data value interface
The data values are sampled at the WBls stage. Here the load, store, MCR, and MRC data is
combined. The memory view of the data is presented, and must be converted back to the register
view depending on the alignment and endianness.
Data is not returned for at least two cycles after the address. However, it is not necessary to
pipeline the address because the slot does not return data for a previous address during this time.
Data values are defined to correspond to the most recent data addresses with the same slot
number, starting from the previous cycle. In other words, data can correspond to an address from
the previous cycle, but not to an address from the same cycle.
Table 15-5 ETMDACTL[17:0]
Bits Reference name Description Qualified by
[17] DANSeq The data transfer is nonsequential from the last. This signal must be
asserted on the first cycle of each instruction, in addition to the second
transfer of a SWP or LDM pc, because the address of these transfers
is not one word greater than the previous transfer, and therefore the
transfer must have its address re-output.
During an unaligned access, this signal is only valid on the first
transfer of the access.
DASlot != 00
[16] DALast The data transfer is the last for this data instruction. This signal is
asserted for both halves of an unaligned access.
A related signal, DAFirst, can be implied from this signal, because the
next transfer must be the first transfer of the next data instruction.
DASlot != 00
[15] DACPRT The data transfer is a CPRT. DASlot != 00
[14] DASwizzle Words must be byte swizzled for ARM big-endian mode. During an
unaligned access, this signal is only valid on the first transfer of the
access.
DASlot != 00
[13:12] DARot Number of bytes to rotate right each word by. During an unaligned
access, this signal is only valid on the first transfer of the access.
DASlot != 00
[11] DAUnaligned First transfer of an unaligned access.
The next transfer must be the second half, where this signal is not
asserted.
DASlot != 00
[10:3] DABLSel Byte lane selects. DASlot != 00
[2] DAWrite Read or write.
During an unaligned access, this signal is only valid on the first
transfer of the access.
DASlot != 00
[1:0] DASlot Slot occupied by data item.
b00 indicates that no slot is in use in this cycle.
b11 indicates that ETM is in use in this cycle.
This slot holds the value even when the ETM is powered down.
None
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