VFP Instruction Execution
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-21
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Table 21-15 lists the pipeline progression of the three instructions.
In Example 21-13 on page 21-20, no data hazards exist between any of the three instructions.
The load multiple is able to begin execution immediately, and data is transferred to the register
file beginning in cycle 6. Because the destination is in bank 0, the FDIVS is a scalar operation
and requires one cycle in the FMAC pipeline E1 stage. If the FDIVS were a short vector
operation, the FADDS might not begin execution until the last FDIVS iteration passed the
FMAC E1 pipeline stage. The FADDS is a short vector operation and requires the FMAC
pipeline E1 stage for cycles 5-8.
Note
E1’ is the first cycle in E1 and is in both FMAC and DS blocks. Subsequent E1 cycles represent
the iteration cycles and occupy both E1 and E2 stages in the DS block.
Table 21-15 Parallel execution in all three pipelines
Instruction cycle number
1234 5 6789101112131415
FLDM DI EM1M2WWWWW- - - - -
FDIVS - DI E1’E1 E1E1E1E1E1E1E1E1E1E1
FADDS - - D I E1 E1 E1 E1 E2 E3 E4 E5 E6 E7 W
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