Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-33
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1.10.1 Extended ARM instruction set summary
Table 1-7 summarizes the extended ARM instruction set.
<iflags>
A sequence of one or more of the following:
a = Set A bit.
i = Set I bit.
f = Set F bit.
If
<effect>
is specified, the sequence determines the interrupt flags that are affected.
<immed_8*4>
A 10-bit constant, formed by left-shifting an 8-bit value by two bits.
<immed_8>
An 8-bit constant.
<immed_8r>
A 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits.
<label>
The target address to branch to.
<LowReg>
Specifies a register in the range R0 to R7.
<mode>
The new mode number for a mode change. See Mode bits on page 2-28.
<op1>
,
<op2>
Specify, in a coprocessor-specific manner, the coprocessor operation to perform.
<operand2>
See Table 1-13 on page 1-43.
<option>
Specifies additional instruction options to the coprocessor. An integer in the range 0 to 255
surrounded by { and }.
<reglist>
A comma-separated list of registers, enclosed in braces {and}.
<rotation>
One of
ROR
#8,
ROR
#16, or
ROR
#24.
<Rm>
Specifies the register, the value of which is the instruction operand.
<Rn>
Specifies the address of the base register.
<shift>
Specifies the optional shift. If present, it must be one of:
•
LSL #N
.
N
must be in the range 0 to 31.
•
ASR #N
.
N
must be in the range 1 to 32.
Table 1-6 Key to instruction set tables (continued)
Symbol Description
Table 1-7 ARM instruction set summary
Operation Assembler
Arithmetic Add
ADD{cond}{S} <Rd>, <Rn>, <operand2>
Add with carry
ADC{cond}{S} <Rd>, <Rn>, <operand2>
Subtract
SUB{cond}{S} <Rd>, <Rn>, <operand2>
Subtract with carry
SBC{cond}{S} <Rd>, <Rn>, <operand2>
Reverse subtract
RSB{cond}{S} <Rd>, <Rn>, <operand2>
Reverse subtract with carry
RSC{cond}{S} <Rd>, <Rn>, <operand2>
Multiply
MUL{cond}{S} <Rd>, <Rm>, <Rs>
Multiply-accumulate
MLA{cond}{S} <Rd>, <Rm>, <Rs>, <Rn>
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