Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-15
ID012310 Non-Confidential, Unrestricted Access
8.5 Data Read/Write Interface transfers
The tables in this section describe the AXI interface behavior for Data Read/Write Interface
transfers for the following interface signals:
• AxBURSTRW[1:0]
• AxLENRW[3:0]
• AxSIZERW[2:0]
• AxADDRRW[31:0]
• WSTRBRW[7:0].
8.5.1 Linefills
A linefill comprises four accesses to the Data Cache if there is no external abort returned. In the
event of an external abort, the doubleword and subsequent doublewords are not written into the
Data Cache and the line is never marked as Valid. The four accesses are:
• Write Tag and data doubleword
• Write data doubleword
• Write data doubleword
• Write Valid = 1, Dirty = 0, and data doubleword.
The linefill can only progress to attempt to write a doubleword if it does not contain dirty data.
This is determined in one of two ways:
• if the victim cache line is not valid, then there is no danger and the linefill progresses
• if the victim line is valid, a signal encodes the doublewords that are clean, either because
they were not dirty or they have been cleaned.
The order of words written into the cache is critical-word first, wrapping at the upper cache line
boundary.
Table 8-12 shows the values of ARADDRRW, ARBURSTRW, ARSIZERW, and
ARLENRW for linefills.
Table 8-12 Linefill behavior on the AXI interface
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00
-
0x07 0x00
Incr 64-bit 4 data transfers
0x08
-
0x0F 0x08
Wrap 64-bit 4 data transfers
0x10
-
0x17 0x10
Wrap 64-bit 4 data transfers
0x18
-
0x1F 0x18
Wrap 64-bit 4 data transfers
To Next Page
Loading...
Need help?
General
