Debug
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-14
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Table 13-7 lists the conditions for generation of a Debug exception or entry into Debug State. In
this table, SBA means Secure Base Address, NSBA means Non-Secure Base Address, MBA
means Monitor Base Address.
Table 13-6 Vector Catch Register bit field definitions
Bits
Read/Write
Attributes
Reset
value
Vector base Description
[31] RW 0 NSBA Vector Catch Enable - FIQ in Non-secure world.
[30] RW 0 NSBA Vector Catch Enable - IRQ in Non-secure world.
[29] DNM/RAZ 0 - Reserved
[28] RW 0 NSBA Vector Catch Enable - Data Abort in Non-secure world.
[27] RW 0 NSBA Vector Catch Enable - Prefetch Abort in Non-secure world.
[26] RW 0 NSBA Vector Catch Enable - SVC in Non-secure world.
[25] RW 0 NSBA Vector Catch Enable - Undefined Instruction in Non-secure
world.
[24:16] DNM/RAZ 0 - Reserved
[15] RW 0 MBA Vector Catch Enable - FIQ in Secure world.
[14] RW 0 MBA Vector Catch Enable - IRQ in Secure world.
[13] DNM/RAZ 0 - Reserved
[12] RW 0 MBA Vector Catch Enable - Data Abort in Secure world.
[11] RW 0 MBA Vector Catch Enable - Prefetch Abort in Secure World
[10] RW 0 MBA Vector Catch Enable - SMC in Secure world.
[9:8] DNM/RAZ 0 - Reserved
[7] RW 0 SBA Vector Catch Enable - FIQ in Secure world.
[6] RW 0 SBA Vector Catch Enable - IRQ in Secure world.
[5] DNM/RAZ 0 - Reserved
[4] RW 0 SBA Vector Catch Enable - Data Abort in Secure world.
[3] RW 0 SBA Vector Catch Enable - Prefetch Abort in Secure world.
[2] RW 0 SBA Vector Catch Enable, SVC in Secure world.
[1] RW 0 SBA Vector Catch Enable, Undefined Instruction in Secure world.
[0] RW 0 SBA Vector Catch Enable, Reset
Table 13-7 Summary of debug entry and exception conditions
VCR bit NS bit, mode VE HIVECS Prefetch vector
VCR[0] = 1 NS bit = 0 or Mode = Secure
Monitor.
X0
0x00000000
1
0xFFFF0000
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