ARM ARM1176JZF-S User Manual

Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-20
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A Noncacheable LDM5 addressing words 4 to 7 is split into two operations as shown in
Table 8-26.
8.5.9 Noncacheable LDM6
The values of ARADDRRW, ARBURSTRW, ARSIZERW, and ARLENRW for
Noncacheable LDM6s addressing words 0 to 2 are shown in:
• Table 8-27 for a load from Strongly Ordered or Device memory
• Table 8-28 on page 8-21 for a load from Noncacheable memory or when the cache is
disabled.
A Noncacheable LDM6 addressing words 3 to 7 is split into two operations as shown in
Table 8-29 on page 8-21.
Table 8-24 Noncacheable LDM5, Strongly Ordered or Device memory
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 32-bit 5 data transfers
0x04 , word 1 0x04 Incr 32-bit 5 data transfers
0x08 , word 2 0x08 Incr 32-bit 5 data transfers
0x0C , word 3 0x0C Incr 32-bit 5 data transfers
Table 8-25 Noncacheable LDM5, Noncacheable memory or cache disabled
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 64-bit 3 data transfers
0x04 , word 1 0x04 Incr 64-bit 3 data transfers
0x08 , word 2 0x08 Incr 64-bit 3 data transfers
0x0C , word 3 0x0C Incr 64-bit 3 data transfers
Table 8-26 Noncacheable LDM5 from word 4, 5, 6, or 7
Address[4:0] Operations
0x10 , word 4 LDM4 from 0x10 + LDR from 0x00
0x14
, word 5 LDM3 from 0x14 + LDM2 from 0x00
0x18
, word 6 LDM2 from 0x18 + LDM3 from 0x00
0x1C
, word 7 LDR from 0x1C + LDM4 from 0x00
Table 8-27 Noncacheable LDM6, Strongly Ordered or Device memory
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 64-bit 3 data transfers
0x04 , word 1 0x04 Incr 32-bit 6 data transfers
0x08 , word 2 0x08 Incr 64-bit 3 data transfers

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English