ARM ARM1176JZF-S - Figure 3-69 Address Mapping with the FCSE PID Register

System Control Coprocessor
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To change the ProcID and perform a fast context switch, write to the FCSE PID Register. You
do not have to flush the contents of the TLB after the switch because the TLB still holds the valid
address tags.
From zero to six instructions after the MCR that writes the ProcID might be fetched with the old
ProcID:
{ProcID = 0}
MOV R0, #1 ; Fetched with ProcID = 0
MCR p15,0,R0,c13,c0,0 ; Fetched with ProcID = 0
A0 (any instruction) ; Fetched with ProcID = 0/1
A1 (any instruction) ; Fetched with ProcID = 0/1
A2 (any instruction) ; Fetched with ProcID = 0/1
A3 (any instruction) ; Fetched with ProcID = 0/1
A4 (any instruction) ; Fetched with ProcID = 0/1
A5 (any instruction) ; Fetched with ProcID = 0/1
A6 (any instruction) ; Fetched with ProcID = 1
Note
You must not rely on this behavior for future compatibility. An IMB must be executed between
changing the ProcID and fetching from locations that are translated by the ProcID.
Addresses issued by the ARM1176JZF-S processor in the range 0-32MB are translated by the
ProcID. Address A becomes A + (ProcID x 32MB). This translated address, the MVA, is used
by the MMU. Addresses higher than 32MB are not translated. The ProcID is a seven-bit field,
enabling 128 x 32MB processes to be mapped.
Note
If ProcID is 0, as it is on Reset, then there is a flat mapping between the ARM1176JZF-S
processor and the MMU.
Figure 3-69 shows how addresses are mapped using the FCSE PID Register.
Figure 3-69 Address mapping with the FCSE PID Register
C13
127
2
1
0
4GB
Modified virtual address (MVA)
input to MMU
Virtual address (VA)
issued by the processor
32MB
0
32MB
0
64MB
4GB