System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-75
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captured on the interrupt is the address of the instruction that launched the cache
clean operation + 4. This enables the standard return mechanism for interrupts to
restart the operation.
If it is essential that the cache is clean, or clean and invalid, for a particular
operation, the sequence of instructions for cleaning, or cleaning and invalidating,
the cache for that operation must handle the arrival of an interrupt at any time
when interrupts are not disabled. This is because interrupts can write to a
previously clean cache. For this reason, the Cache Dirty Status Register indicates
if the cache has been written to since the last clean of the cache was started, see
Cache Dirty Status Register on page 3-78. You can interrogate the Cache Dirty
Status Register to determine if the cache is clean, and if this is done while
interrupts are disabled, the following operations can rely on having a clean cache.
The following sequence shows this approach:
; interrupts are assumed to be enabled at this point
Loop1 MOV R1, #0
MCR CP15, 0, R1, C7, C10, 0 ; Clean (or Clean & Invalidate) Cache
MRS R2, CPSR
CPSID iaf ; Disable interrupts
MRC CP15, 0, R1, C7, C10, 6 ; Read Cache Dirty Status Register
ANDS R1, R1, #1 ; Check if it is clean
BEQ UseClean
MSR CPSR, R2 ; Re-enable interrupts
B Loop1 ; - clean the cache again
UseClean Do_Clean_Operations ; Perform whatever operation relies on
; the cache being clean/invalid.
; To reduce impact on interrupt
; latency, this sequence should be
; short
MSR CPSR, R2 ; Re-enable interrupts
The long cache clean operation is performed with interrupts enabled throughout
this routine.
Single cache lines
There are two ways to perform invalidate or clean operations on cache lines:
• by use of Set and Index format
• by use of MVA format.
Table 3-72 lists the instructions and operations that you can use for single cache
lines.
Table 3-72 Cache operations for single lines
Instruction Data Function
MCR p15, 0, <Rd>, c7, c5, 1
MVA Invalidate Instruction Cache Line, using MVA
MCR p15, 0, <Rd>, c7, c5, 2
Set/Index Invalidate Instruction Cache Line, using Index
MCR p15, 0, <Rd>, c7, c6, 1
MVA Invalidate Data Cache Line, using MVA
MCR p15, 0, <Rd>, c7, c6, 2
Set/Index Invalidate Data Cache Line, using Index
MCR p15, 0, <Rd>, c7, c10, 1
MVA Clean Data Cache Line, using MVA
MCR p15, 0, <Rd>, c7, c10, 2
Set/Index Clean Data Cache Line, using Index
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