System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-35
ID012310 Non-Confidential, Unrestricted Access
Table 3-25 lists the results of attempted access for each mode.
To use the Memory Model Feature Register 2 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 6.
For example:
MRC p15, 0, <Rd>, c0, c1, 6 ;Read Memory Model Feature Register 2.
c0, Memory Model Feature Register 3
The purpose of the Memory Model Feature Register 3 is to provide information about the
memory model, memory management, cache support, and TLB operations of the processor.
The Memory Model Feature Register 3 is:
•in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-20 shows the bit arrangement for Memory Model Feature Register 3.
Figure 3-20 Memory Model Feature Register 3 format
Table 3-26 lists how the bit values correspond with the Memory Model Feature Register 3
functions.
Table 3-25 Results of access to the Memory Model Feature Register 2
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Undefined exception Data Undefined exception Undefined exception
ReservedReservedReservedReservedReserved - -Reserved
31 8 7 4 3 0
16 15 12 1128 27 24 23 20 19
Table 3-26 Memory Model Feature Register 3 bit functions
Bits Field name Function
[31:8] - Reserved. RAZ.
[7:4] - Support for hierarchical cache maintenance by MVA, all architectures
0x0
, no support in ARM1176JZF-S processors.
[3:0] - Support for hierarchical cache maintenance by Set/Way, all architectures.
0x0
, no support in ARM1176JZF-S processors.
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