Unaligned and Mixed-endian Data Access Support
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-7
ID012310 Non-Confidential, Unrestricted Access
Figure 4-3 Store byte
4.3.4 Load unsigned halfword, little-endian
The addressed byte-pair is loaded from memory into the low 16 bits of the general-purpose
register, and the upper 16 bits are zeroed so that the least-significant addressed byte in memory
appears in bits [7:0] of the ARM register, as Figure 4-4 shows.
Figure 4-4 Load unsigned halfword, little-endian
If strict alignment fault checking is enabled and Address bit 0 is not zero, then a Data Abort is
generated and the MMU returns a Misaligned fault in the Fault Status Register.
4.3.5 Load unsigned halfword, big-endian
The addressed byte-pair is loaded from memory into the low 16 bits of the general-purpose
register, and the upper 16 bits are zeroed so that the most-significant addressed byte in memory
appears in bits [15:8] of the ARM register, as Figure 4-5 on page 4-8 shows.
Register
31 23 15 7 0
x x x b b
Memory
Address
A[31:0]
70
b1
b0
Memory Register
31 23 15 7 0
Address
A[31:0]
70
0 0 b1 b0
+1 msbyte
lsbyte
To Next Page
Loading...
Need help?
General
