Level Two Interface
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AxCACHE[3:0]
The AxCACHE[3:0] signals indicate the bufferable, cacheable, write-through, write-back, and
allocate attributes of the transaction. These attributes are for the level two memory system.
Table 8-6 shows the correspondence between the AxCACHE[3:0] encoding and TLB
cacheable attributes.
AxPROT[2:0]
The AxPROT[2:0] signal indicates the protection level of the transaction, that is if the
transaction is:
• normal or privileged
• Secure or Non-secure
• Data access or Instruction access.
All transactions from the instruction port are marked as instruction accesses, ARPROTI[2] = 1.
Transactions from the DMA port are marked as instruction accesses, AxPROTD[2] = 1, if the
transaction is to or from the Instruction TCM, and as data accesses, AxPROTD[2] = 0, for
transfers to or from the Data TCM.
Transactions on the peripheral and data read/write ports are marked as data accesses.
Table 8-7 shows the supported values for AxPROT[2:0].
Table 8-6 AxCACHE[3:0] encoding
AxCACHE[3:0] Transaction attributes
b0000 Strongly ordered
b0001 Shared device or non-shared device
b0010 Outer noncacheable
b0110 Outer write-through, no allocate on write
b0111 Outer write-back, no allocate on write
b1111 Outer write-back, write allocate.
Table 8-7 AxPROT[2:0] encoding
Signal Description
AxPROT[2] 0 = Data access
1 = Instruction access
AxPROT[1] 0 = Secure
1 = Non-secure
AxPROT[0] 0 = Normal, User
1 = Privileged
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