Level Two Interface
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• WIDD.
When you connect the processor in an AXI system, you can choose whatever ID value suits your
system. The only requirement is that AWI D and WID must have the same value.
8.1.1 AXI parameters for the level 2 interconnect interfaces
Table 8-1 shows the AXI parameters for the level 2 interconnect interfaces.
8.1.2 Level two instruction-side controller
The level two instruction-side controller contains the level two Instruction Fetch Interface. See
Instruction Fetch Interface.
The level two instruction-side controller handles all instruction-side cache misses including
those for Noncacheable locations. It is responsible for the sequencing of cache operations for
Instruction Cache linefills, making requests for the individual stores through the Prefetch Unit
(PU) to the Instruction Cache. The decoupling involved means that the level two instruction-side
controller contains some buffering.
Instruction Fetch Interface
The Instruction Fetch Interface is a read-only interface that services the Instruction Cache on
cache misses, including the fetching of instructions for the PU that are held in memory marked
as Noncacheable. The interface is optimized for cache linefills rather than individual requests.
8.1.3 Level two data-side controller
The level two data-side controller is responsible for the level two:
• Data Read/Write Interface
• Peripheral Interface.
Table 8-1 AXI parameters for the level 2 interconnect interfaces
Parameter
Interface:
Instruction, RO Data, RW Peripheral, RW DMA, RW
Write Issuing Capability Not applicable 2 1 1
Read Issuing Capability 2 2 1 1
Combined Issuing Capability Not applicable 4 1 1
Write ID Capability Not applicable 1 1 1
Write Interleave Capability Not applicable
1
a
1
a
1
a
Write ID Width
Not applicable
b
Not applicable
b
Not applicable
b
Not applicable
b
Read ID Capability 1 1 1 1
Read ID Width
Not applicable
b
Not applicable
b
Not applicable
b
Not applicable
b
a. The value of 1 means that interleaving or re-ordering cannot occur.
b. The level 2 interconnect interfaces do not implement any AXI ID signals.
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