System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-126
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3.2.46 c13, FCSE PID Register
The c13, Context ID Register on page 3-128 replaces the FCSE PID Register. Use of the FCSE
PID Register is deprecated.
The FCSE PID Register is:
• in CP15 c13
• a 32-bit read/write register banked for Secure and Non-secure worlds
• accessible in privileged modes only.
Writing to this register globally flushes the BTAC.
Figure 3-68 shows the arrangement of bits in the register.
Figure 3-68 FCSE PID Register format
Table 3-127 lists how the bit values correspond with the FCSE PID Register functions.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Table 3-128 lists the results of attempted access for each mode.
To use the FCSE PID Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c13
• CRm set to c0
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c13, c0, 0 ; Read FCSE PID Register
MCR p15, 0, <Rd>, c13, c0, 0 ; Write FCSE PID Register
FCSE PID
31 25 24 0
SBZ
Table 3-127 FCSE PID Register bit functions
Bits Field name Function
[31:25] FCSE PID The purpose of the FCSE PID Register is to provide the ProcID for fast context switch memory
mappings. The MMU uses the contents of this register to map memory addresses in the range
0-32MB.
Identifies a specific process for fast context switch.
Holds the ProcID. The reset value is 0.
[24:0] - Reserved.
SBZ.
Table 3-128 Results of access to the FCSE PID Register
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Secure data Secure data Non-secure data Non-secure data Undefined exception
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