Debug
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-24
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Table 13-18 Debug State MMU Control Register bit functions
Bits Reset value Name Description
[31:7] UNP/SBZ - Reserved
[6] 0 nDMM 1 = Normal operation of Main TLB matching in Debug state.
0 = Main TLB match disabled in Debug state.
[5] UNP/SBZ - Reserved
[4] 0 nDML 1 = Normal operation of Main TLB loading in Debug state.
0 = Main TLB load disabled in Debug state.
[3] 0 nIUM 1 = Normal operation of Instruction Micro TLB matching in Debug state.
0 = Instruction Micro TLB match disabled in Debug state.
[2] 0 nDUM 1 = Normal operation of Data Micro TLB matching in Debug state.
0 = Data Micro TLB match disabled in Debug state.
[1] 0 nIUL 1 = Normal operation of Instruction Micro TLB loading and flushing in Debug state.
0 = Instruction Micro TLB load and flush disabled in Debug state.
[0] 0 nDUL 1 = Normal operation of Data Micro TLB loading and flushing in Debug state.
0 = Data Micro TLB load and flush disabled in Debug state.
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