Unaligned and Mixed-endian Data Access Support
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-19
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Mixed-endian configuration supported
This behavior is enabled when the U bit in CP15 Register c1 is set. This is only supported when
the B bit in CP15 Register c1 is reset, as Table 4-5 lists.
4.5.3 Reset values of the U, B, and EE bits
Table 4-6 lists the reset values of the BIGENDINIT and UBITINIT pins that determine the
values of the U, B, and EE bits at reset. The pins determine the reset value of the B bit and both
the Secure and Non-secure reset values of the U and EE bits.
Table 4-5 Mixed-endian configuration
UBE
Instruction
endianness
Data
endianness
Description
1 0 0 LE LE LE instructions, little-endian data load/store. Unaligned data access
permitted.
1 0 1 LE BE-8 LE instructions, big-endian data load/store. Unaligned data access
permitted.
1 1 0 BE-32 BE-32 Legacy BE instructions/data.
1 1 1 - - Reserved.
Table 4-6 B bit, U bit, and EE bit settings
BIGENDINIT UBITINIT B U EE
00000
01010
10100
11011
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