Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-37
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Return From Exception (RFE)
This instruction loads the PC and CPSR from sequential addresses. This is used to return from
an exception that has had its return state saved using the SRS instruction, see Store Return State
(SRS) on page 2-36, and again uses a version of an ARM addressing mode, modified to assume
a {PC,CPSR} register list.
Change Processor State (CPS)
This instruction provides new values for the CPSR interrupt masks, mode bits, or both, and is
designed to shorten and speed up the read/modify/write instruction sequence used in ARMv5 to
perform such tasks. Together with the SRS instruction, it enables an exception handler to save
its return information on the stack of another mode and then switch to that other mode, without
modifying the stack belonging to the original mode or any registers other than the new mode
stack pointer.
This instruction also streamlines interrupt mask handling and mode switches in other code. In
particular it enables short code sequences to be made atomic efficiently in a uniprocessor system
by disabling interrupts at their start and re-enabling interrupts at their end. A similar Thumb
instruction is also provided. However, the Thumb instruction can only change the interrupt
masks, not the processor mode as well, to avoid using too much instruction set space.
2.12.2 Exception entry and exit summary
Table 2-8 summarizes the PC value preserved in the relevant R14 on exception entry, and the
recommended instruction for exiting the exception handler. Full details of Jazelle state
exceptions are provided in the Jazelle V1 Architecture Reference Manual.
Table 2-8 Exception entry and exit
Exception
or entry
Return instruction
Previous state
Notes
ARM R14_x
Thumb
R14_x
Jazelle
R14_x
SVC
MOVS PC, R14_svc
PC + 4 PC+2 - Where the PC is the address
of the SVC, SMC, or
undefined instruction. Not
used in Jazelle state.
SMC
MOVS PC, R14_mon
PC + 4 - -
UNDEF
MOVS PC, R14_und
PC + 4 PC+2 -
PAB T
SUBS PC, R14_abt, #4
PC + 4 PC+4 PC+4 Where the PC is the address
of instruction that had the
Prefetch Abort.
FIQ
SUBS PC, R14_fiq, #4
PC + 4 PC+4 PC+4 Where the PC is the address
of the instruction that was
not executed because the
FIQ or IRQ took priority.
IRQ
SUBS PC, R14_irq, #4
PC + 4 PC+4 PC+4
DABT
SUBS PC, R14_abt, #8
PC + 8 PC+8 PC+8 Where the PC is the address
of the Load or Store
instruction that generated
the Data Abort.
RESET
NA
- - - The value saved in R14_svc
on reset is Unpredictable.
BKPT
SUBS PC, R14_abt, #4
PC + 4 PC+4 PC+4 Software breakpoint.
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