ARM ARM1176JZF-S User Manual

Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-17
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8.5.4 Noncacheable LDR or LDM1
Table 8-15 shows the values of ARADDRRW, ARBURSTRW, ARSIZERW, and
ARLENRW for Noncacheable LDRs or LDM1s.
8.5.5 Noncacheable LDRD or LDM2
Table 8-16 shows the values of ARADDRRW, ARBURSTRW, ARSIZERW, and
ARLENRW for Noncacheable LDRDs or LDM2s addressing words 0 to 6.
A Noncacheable LDRD or LDM2 addressing word 7 is split into two LDRs, as shown in
Table 8-17 on page 8-18.
Table 8-15 Noncacheable LDR or LDM1
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , byte 0, word 0 0x00 Incr 32-bit 1 data transfer
0x01 , byte 1 0x01 Incr 32-bit 1 data transfer
0x04 Incr 8-bit 1 data transfer
0x02 , byte 2 0x02 Incr 16-bit 1 data transfer
0x04 Incr 16-bit 1 data transfer
0x03 , byte 3 0x03 Incr 8-bit 1 data transfer
0x04 Incr 32-bit 1 data transfer
0x04 , byte 4, word 1 0x04 Incr 32-bit 1 data transfer
0x05 , byte 5 0x05 Incr 32-bit 1 data transfer
0x08 Incr 8-bit 1 data transfer
0x06 , byte 6 0x06 Incr 16-bit 1 data transfer
0x08 Incr 16-bit 1 data transfer
0x07 , byte 7 0x07 Incr 8-bit 1 data transfer
0x08 Incr 32-bit 1 data transfer
Table 8-16 Noncacheable LDRD or LDM2
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 64-bit 1 data transfer
0x04 , word 1 0x04 Incr 32-bit 2 data transfers
0x08 , word 2 0x08 Incr 64-bit 1 data transfer
0x0C , word 3 0x0C Incr 32-bit 2 data transfers
0x10 , word 4 0x10 Incr 64-bit 1 data transfer
0x14 , word 5 0x14 Incr 32-bit 2 data transfers
0x18 , word 6 0x18 Incr 64-bit 1 data transfer

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English