Coprocessor Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-7
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Each pipeline stage contains a decoded instruction, and a tag, plus a few status flags:
Full flag This flag is set whenever the pipeline stage contains an instruction.
Dead flag This flag is set to indicate that the instruction in the stage is a phantom. See
Cancel operations on page 11-19.
Tail flag This flag is set to indicate that the instruction is the tail of an iterated instruction.
See Loads on page 11-16.
There might also be other flags associated with the decoding of the instruction. Each stage is
controlled not only by its own state, but also by external signals and signals from the following
state, as follows:
Stall This signal prevents the stage from accepting a new instruction or passing its own
instruction on, and only affects the D, I, Ex1, and Ex6 stages.
Iterate This signal indicates that the instruction in the stage must be iterated to implement
a multiple load/store and only applies to the I stage.
Enable This signal indicates that the next stage in the pipeline is ready to accept data from
the current stage.
These signals are combined with the current state of the pipeline to determine if the stage can
accept new data, and what the new state of the stage is going to be. Table 11-3 lists how the new
state of the pipeline stage is derived.
The Enable input comes from the next stage in the pipeline and indicates if data can be passed
on. In general, if this signal is unasserted the pipeline stage cannot receive new data or pass on
its own contents. However, if the pipeline stage is empty it can receive new data without passing
any data on to the next stage. This is known as bubble closing, because it has the effect of filling
up empty stages in the pipeline by enabling them to move on while lower stages are stalled.
11.2.5 Instruction tagging
It is sometimes necessary for the core to be able to identify instructions in the coprocessor
pipeline. This is necessary for flushing, see Flush operations on page 11-19, so that the core can
indicate to the coprocessor the instructions that are to be flushed. The core therefore gives each
instruction sent to the coprocessor a tag, that is drawn from a pool of values large enough so that
all the tags in the pipeline at any moment are unique. Sixteen tags are sufficient to achieve this,
requiring a four-bit tag field. Each time a tag is assigned to an instruction, the tag number is
incremented modulo 16 to generate the next tag.
Table 11-3 Pipeline stage update
Stall Enable input Iterate State Enable To next stage Remarks
0 0 X Empty 1 None Bubble closing
0 0 X Full 0 - Stalled by next stage
0 1 0 Empty 1 None Normal pipeline movement
0 1 0 Full 1 Current Normal pipeline movement
0 1 1 Empty - - Impossible
0 1 1 Full 0 Current Iteration, I stage only
1 X X X 0 None Stalled, D, I, Ex1, and Ex6 only
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