System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-25
ID012310 Non-Confidential, Unrestricted Access
For example:
MRC p15,0,<Rd>,c0,c0,2 ; returns TCM status register
3.2.5 c0, TLB Type Register
The purpose of the TLB Type Register is to return the number of lockable entries for the TLB.
The TLB has 64 entries organized as a unified two-way set associative TLB. In addition, it has
eight lockable entries that the read-only TLB Type Register specifies.
The TLB Type Register is:
•in CP15 c0
• a 32-bit read only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-13 shows the bit arrangement for the TLB Type Register.
Figure 3-13 TLB Type Register format
Table 3-10 lists how the bit values correspond with the TLB Type Register functions.
Table 3-11 lists the results of attempted access for each mode.
To use the TLB Type Register read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c0
• Opcode_2 set to 3.
USBZ/UNP
31 24 23 16 15 8 7 1 0
ILsize DLsize SBZ/UNP
Table 3-10 TLB Type Register bit functions
Bits Field name Function
[31:24] - UNP/SBZ
[23:16] ILsize Instruction lockable size specifies the number of instruction TLB lockable entries
0, indicates that the ARM1176JZF-S processor has a unified TLB
[15:8] DLsize Data lockable size specifies the number of unified or data TLB lockable entries
0x08
, indicates the ARM1176JZF-S processors has 8 unified TLB lockable entries
[7:1] - UNP/SBZ
[0] U Unified specifies if the TLB is unified, 0, or if there are separate instruction and data TLBs, 1.
0, indicates that the ARM1176JZF-S processor has a unified TLB
Table 3-11 Results of access to the TLB Type Register
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Undefined exception Data Undefined exception Undefined exception
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