AC Characteristics
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 17-3
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17.2 Processor timing parameters
The maximum timing parameter or constraint delay for each processor signal applied to the SoC
is given as a percentage in Table 17-1 to Table 17-8 on page 17-6. The input delay columns
provide the maximum and minimum time as a percentage of the processor clock cycle given to
the SoC for that signal.
Note
The maximum delay timing parameter or constraint permitted for all processor output signals
enables 60% of the processor clock cycle to the SoC.
Table 17-1 lists the global signal timing parameters.
Table 17-2 lists the AXI interface timing parameters.
Table 17-1 Global signals
Name Minimum input delay Maximum input delay%
ACLKEND Clock uncertainty 40
ACLKENI Clock uncertainty 40
ACLKENP Clock uncertainty 40
ACLKENRW Clock uncertainty 40
ARESETDn Clock uncertainty 20
ARESETIn Clock uncertainty 20
ARESETPn Clock uncertainty 20
ARESETRWn Clock uncertainty 20
nPORESETIN Clock uncertainty 20
nRESETIN Clock uncertainty 20
nVFPRESETIN Clock uncertainty 20
RAMCLAMP Clock uncertainty 20
SYNCMODEREQD Clock uncertainty 60
SYNCMODEREQI Clock uncertainty 60
SYNCMODEREQP Clock uncertainty 60
SYNCMODEREQRW Clock uncertainty 60
VFPCLAMP Clock uncertainty 20
Table 17-2 AXI signals
Name Minimum input delay Maximum input delay%
ARREADYD Clock uncertainty 50
ARREADYI Clock uncertainty 50
ARREADYP Clock uncertainty 50
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