VFP Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-11
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20.3.4 FMRRS
FMRRS transfers data in two consecutively numbered single-precision VFP11 registers to two
ARM11 registers. The ARM11 registers do not have to be contiguous. Figure 20-4 shows the
format of the FMRRS instruction.
Figure 20-4 FMRRS instruction format
Syntax
FMRRS {<cond>} <Rd>, <Rn>, <registers>
where:
<cond>
Is the condition under which the instruction is executed. If <cond> is omitted, the
AL, always, condition is used.
<Rd>
Specifies the destination ARM11 register for the Sm VFP11 coprocessor
single-precision value.
<Rn>
Specifies the destination ARM11 register for the S(m + 1) VFP11 coprocessor
single-precision value.
<registers>
Specifies the pair of consecutively numbered single-precision VFP11 source
registers, separated by a comma and surrounded by brackets. If m is the number
of the first register in the list, the list is encoded in the instruction by setting Sm
to the top four bits of m and M to the bottom bit of m. For example, if
<registers>
is {S16, S17}, the Sm field of the instruction is b1000 and the M bit is 0.
Architecture version
All
Exceptions
None
Operation
If ConditionPassed(cond) then
Rd = Sm
Rn = S(m + 1)
Notes
Conversions In the programmer’s model, FMRRS does not perform any conversion of
the value transferred. Arithmetic instructions using Rd and Rn treat the
contents as an integer, whereas most VFP11 instructions treat the Sm and
S(m + 1) values as single-precision floating-point numbers.
Invalid register lists
If Sm is b1111 and M is 1, an encoding of S31, the instruction is
Unpredictable.
Use of R15 If R15 is specified for Rd or Rn, the results are Unpredictable.
1 1 0 0 0 1 0 1 Rn Rd 1 0 1 0 0 0 M 1 Sm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond
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