VFP Instruction Execution
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-16
ID012310 Non-Confidential, Unrestricted Access
21.8 Data hazards in RunFast mode
In RunFast mode, source registers for the FMAC and FMUL family of instructions are locked:
• when the vector length exceeds four iterations in single-precision instructions
• when the vector length exceeds two iterations in double-precision instructions.
No source registers are locked for scalar instructions.
21.8.1 Short vector CDP-load multiple WAR hazard example
Example 21-9 is the same as Example 21-8 on page 21-15. The LEN field contains b011,
selecting a vector length of four iterations, and the STRIDE field contains b00, selecting a vector
stride of one. Executing these instructions in RunFast mode reduces the cycle count of the
FLDMS by four cycles.
Example 21-9 Short vector FMULS-FLDMS WAR hazard in RunFast mode
FMULS S8, S16, S24
FLDMS R2, {S16-S27}
Table 21-11 shows that the VFP11 coprocessor does not stall the FLDMS operation.
Table 21-11 Short vector FMULS-FLDMS WAR hazard in RunFast mode
Instruction cycle number
Instruction12345 6 78910111213
FMULS DI E1E1E1 E1 E2E3E4E5E6E7W
FLDMS - DI E M1M2WWWWWW-
To Next Page
Loading...
