Cycle Timings and Interlock Behavior
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-16
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16.10 Single load and store instructions
This section describes the cycle timing behavior for LDR, LDRT,LDRB, LDRBT, LDRSB,
LDRH, LDRSH, LDREX, LDREXB, LDREXH, LDREXD, STR, STRT, STRB, STRBT,
STRH, STREX, STREXB, STREXH, STREXD and PLD instructions.
Table 16-13 lists the cycle timing behavior for stores and loads, other than loads to the PC. You
can replace LDR with any of the above single load or store instructions. The following rules
apply:
• They are single-cycle issue if a constant offset is used or if a register offset with no shift,
or shift by 2 is used. Both the base and any offset register are Early Regs.
• They are two-cycle issue if either a negative register offset or a shift other than LSL #2 is
used. Only the offset register is an Early Reg.
• If ARMv6 unaligned support is enabled then accesses to addresses not aligned to the
access size generates two memory accesses, and so consume the load/store unit for an
additional cycle. This extra cycle is required if the base or the offset is not aligned to the
access size, consequently the final address is potentially unaligned, even if the final
address turns out to be aligned.
• If ARMv6 unaligned support is enabled and the final access address is unaligned there is
an extra cycle of result latency.
• PLD, data preload hint instructions, have cycle timing behavior as for load instructions.
Because they have no destination register, the result latency is not-applicable for such
instructions. Because a PLD instruction is treated as any other load instruction by all
levels of cache, standard data-dependency rules and eviction procedures are followed. The
PLD instruction is ignored in case of an address translation fault, a cache hit, or an abort,
during any stage of PLD execution. Only use the PLD instruction to preload from
cacheable Normal memory.
• The updated base register has a result latency of one. For back-to-back load/store
instructions with base write back, the updated base is available to the following load/store
instruction with a result latency of 0.
Table 16-13 Cycle timing behavior for stores and loads, other than loads to the PC
Example instruction
Cycle
s
Memory cycles Result latency Comments
LDR <Rd>, <addr_md_1cycle>
a
1 1 3 Legacy access / ARMv6 aligned
access
LDR <Rd>, <addr_md_2cycle>
a
2 2 4 Legacy access / ARMv6 aligned
access
LDR <Rd>, <addr_md_1cycle>
a
1 2 3 Potentially ARMv6 unaligned
access
LDR <Rd>, <addr_md_2cycle>
a
2 3 4 Potentially ARMv6 unaligned
access
LDR <Rd>, <addr_md_1cycle>
a
1 2 4 ARMv6 unaligned access
LDR <Rd>, <addr_md_2cycle>
a
1 2 4 ARMv6 unaligned access
a. See Table 16-15 on page 16-17 for an explanation of
<addr_md_1cycle>
and
<addr_md_2cycle>
.
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