System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-21
ID012310 Non-Confidential, Unrestricted Access
To use the Main ID Register read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c0
• Opcode_2 set to 0.
For example:
MRC p15,0,<Rd>,c0,c0,0 ;Read Main ID Register
For more information on the processor features, see c0, CPUID registers on page 3-26.
3.2.3 c0, Cache Type Register
The purpose of the Cache Type Register is to provide information about the size and architecture
of the cache for the operating system. This enables the operating system to establish how to
clean the cache and how to lock it down. Inclusion of this register enables RTOS vendors to
produce future-proof versions of their operating systems.
The Cache Type Register is:
•in CP15 c0
• a 32-bit read only register, common to Secure and Non-secure worlds
• accessible in privileged modes only.
All ARMv4T and later cached processors contain this register. Figure 3-11 shows the
arrangement of bits in the Cache Type Register.
Figure 3-11 Cache Type Register format
Table 3-6 lists how the bit values correspond with the Cache Type Register functions.
0
31
30
29 28 25 24 23 12 11 0
0 0 Ctype S P 0 Size Assoc M LenP 0 Size Assoc M Len
Dsize Isize
22 21 18 17 15 14 13 10 9 6 5 3 2 1
Table 3-6 Cache Type Register bit functions
Bits Field name Function
[31:29] - 0
[28:25] Ctype The Cache type and Separate bits provide information about the cache architecture.
b1110, indicates that the ARM1176JZF-S processor supports:
• write back cache
• Format C cache lockdown
• Register 7 cache cleaning operations.
[24] S bit S = 1, indicates that the processor has separate instruction and data caches and not a unified
cache.
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