System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-29
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c0, Debug Feature Register 0
The purpose of the Debug Feature Register 0 is to provide information about the debug system
for the processor.
Debug Feature Register 0 is:
•in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-16 shows the bit arrangement for Debug Feature Register 0.
Figure 3-16 Debug Feature Register 0 format
Table 3-16 lists how the bit values correspond with the Debug Feature Register 0 functions.
Table 3-17 lists the results of attempted access for each mode.
To use the Debug Feature Register 0 read CP15 with:
• Opcode_1 set to 0
Reserved ---Reserved
31 12 11 8 7 4 3 0
- - -
24 23 20 19 16 1528 27
Table 3-16 Debug Feature Register 0 bit functions
Bits Field name Function
[31:28] - Reserved. RAZ.
[27:24] - Reserved. RAZ.
[23:20] - Indicates the type of memory-mapped microcontroller debug model that the processor
supports.
0x0
, ARM1176JZF-S processors do not support this debug model.
[19:16] - Indicates the type of memory-mapped Trace debug model that the processor supports.
0x0
, ARM1176JZF-S processors do not support this debug model.
[15:12] - Indicates the type of coprocessor-based Trace debug model that the processor supports.
0x0
, ARM1176JZF-S processors do not support this debug model.
[11:8] - Indicates the type of embedded processor debug model that the processor supports.
0x0
, ARM1176JZF-S processors do not support this debug model.
[7:4] - Indicates the type of Secure debug model that the processor supports.
0x3
, ARM1176JZF-S processors support the v6.1 Secure debug architecture based model.
[3:0] - Indicates the type of applications processor debug model that the processor supports.
0x3
, ARM1176JZF-S processors support the v6.1 debug model.
Table 3-17 Results of access to the Debug Feature Register 0
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Undefined exception Data Undefined exception Undefined exception
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