Level One Memory System
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 7-12
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7.5 TCM and cache interactions
In the event that a TCM and a cache both contain the requested address, it is architecturally
Unpredictable which memory the instruction data is returned from. It is expected that such an
event only arises from a failure to invalidate the cache when the base register of the TCM is
changed, and so is clearly a programming error. For a Harvard arrangement of caches and TCM,
data reads and writes can access any Instruction TCM for both reads and writes. This ensures
that accesses to literal pools, Undefined instructions, and SVC numbers are possible, and aids
debugging. For this reason, an Instruction TCM must behave as a unified TCM, but can be
optimized for instruction fetches.
You must not program an Instruction TCM to the same base address as a Data TCM and, if the
two RAMs are different sizes, the regions in physical memory of the two RAMs must not be
overlapped. This is because the resulting behavior is architecturally Unpredictable.
In these cases, you must not rely on the behavior of ARM1176JZF-S processor for code that is
intended to be ported to other ARM platforms.
In all cases, no security consideration is necessary because there cannot be a conflict between
accesses targeting Secure and Non-secure memory. Any cache line or TCM data is marked as
being Secure or Non-secure and no Unpredictable situations can result from this.
7.5.1 Overlapping between TCM regions
Where TCM regions overlap, the access priority is worked out using these rules, starting with
the highest priority rule:
1. Where there is an overlap between a DTCM and an ITCM, the DTCM has priority for data
accesses.
Note
Instruction accesses to the DTCM are not possible.
2. Where there is an overlap between two TCMs on the same side, TCM0 has priority. This
means that DTCM0 has priority over DTCM1, and ITCM0 has priority over ITCM1.
This means that, for data accesses, the priority order if all four TCMs overlap is:
1. DTCM0, highest priority
2. DTCM1
3. ITCM0
4. ITCM1, lowest priority.
For instruction accesses, the priority order is:
1. ITCM0, highest priority
2. ITCM1, lowest priority.
These priority rules are not affected by whether the TCMs are Secure or Non-secure. The only
effect of configuring TCMs as Secure or Non-secure is that a Secure TCM cannot overlap a
Non-secure TCM.
7.5.2 DMA and core access arbitration
DMA and core accesses to both the Instruction TCM and the Data TCM can occur in parallel.
So as not to disrupt the execution of the core, core-generated accesses have priority over those
requested by the DMA engine, regardless of the security level of the accesses.
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