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Memory Management Unit

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6.9 MMU fault checking

During the processing of a section or page, the MMU behaves differently because it is checking

for faults. The MMU can generate these faults:

• Alignment fault on page 6-32

• Translation fault on page 6-32

• Access bit fault on page 6-32

• Domain fault on page 6-33

• Permission fault on page 6-33.

Aborts that are detected by the MMU are taken before any external memory access takes place.

Alignment fault checking is enabled by the A bit in the Control Register CP15, This bit is

duplicated in the Secure and Non-secure worlds for the support of TrustZone. Alignment fault

checking is independent of the MMU being enabled. Translation, Access bit, domain, and

permission faults are only generated when the MMU is enabled.

The access control mechanisms of the MMU detect the conditions that produce these faults. If

a fault is detected as the result of a memory access, the MMU aborts the access and signals the

fault condition to the processor. The MMU retains status and address information about faults

generated by data accesses in DFSR and FAR, see Fault status and address on page 6-34. The

MMU does not retain status about faults generated by instruction fetches.

An access violation for a given memory access inhibits any corresponding external access, and

an abort is returned to the processor.

ARM ARM1176JZF-S User Manual

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