System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-27
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Table 3-13 lists the results of attempted access for each mode.
To use the Processor Feature Register 0 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c0, c1, 0 ;Read Processor Feature Register 0
c0, Processor Feature Register 1
The purpose of the Processor Feature Register 1 is to provide information about the execution
state support and programmer’s model for the processor.
Processor Feature Register 1 is:
•in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-15 on page 3-28 shows the bit arrangement for Processor Feature Register 1.
[19:16] - Reserved. RAZ.
[15:12] State3
Indicates support for Thumb-2
™
execution environment.
0x0
, ARM1176JZF-S processors do not support Thumb-2.
[11:8] State2 Indicates support for Java extension interface.
0x1
, ARM1176JZF-S processors support Java.
[7:4] State1 Indicates type of Thumb encoding that the processor supports.
0x1
, ARM1176JZF-S processors support Thumb-1 but do not support Thumb-2.
[3:0] State0 Indicates support for 32-bit ARM instruction set.
0x1
, ARM1176JZF-S processors support 32-bit ARM instructions.
Table 3-12 Processor Feature Register 0 bit functions (continued)
Bits Field name Function
Table 3-13 Results of access to the Processor Feature Register 0
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Undefined exception Data Undefined exception Undefined exception
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