VFP Exception Handling
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-24
ID012310 Non-Confidential, Unrestricted Access
22.12.7 FCPY, FABS, and FNEG
It is not possible for FCPY, FABS, or FNEG to bounce for any operand.
22.12.8 FCVTDS and FCVTSD
Only the FCVTSD operation is capable of overflow or underflow. To reduce logic complexity,
the overflow ranges are the same as the LSA ranges. Table 22-11 lists the FCVTSD bounce
conditions. The exponent values that Table 22-11 lists are in biased format.
22.12.9 FUITO and FSITO
It is not possible to generate overflow or underflow in an integer-to-float conversion.
22.12.10FTOUI, FTOUIZ, FTOSI, and FTOSIZ
Float-to-integer conversions generate Invalid Operation exceptions rather than Overflow or
Underflow exceptions. To support signed conversions with round-towards-zero rounding in the
maximum range possible for C, C++, and Java compiled code, the thresholds for pessimistic
bouncing are different for the various rounding modes.
Table 22-12 on page 22-25 and Table 22-13 on page 22-26 use the following notation:
In the VFP Response column, the response notations are:
all These input values are bounced for all rounding modes.
S These input values are bounced for signed conversions in all rounding modes.
SnZ These input values are bounced for signed conversions in all rounding modes
except round-towards-zero.
U These input values are bounced for unsigned conversions in all rounding modes.
UnZ These input values are bounced for unsigned conversions in all rounding modes
except round-towards-zero.
Table 22-11 FCVTSD bounce thresholds
Double-precision operand
exponent value Float value
FCVTSD condition in full-compliance
mode
>
0x47F
SP
a
overflow
Bounce
0x47F
SP NaN or infinity Bounce
0x47E
SP maximum normal Bounce
0x47D
SP normal Bounce
0x47C
SP normal Normal
0x3FF
e = 0 bias value Normal
0x381
SP normal Normal
0x380
SP subnormal Bounce
<
0x380
SP underflow Bounce
a. SP = single-precision.
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