Unaligned and Mixed-endian Data Access Support
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-11
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Figure 4-11 Load word, big-endian
If strict alignment fault checking is enabled and Address bits [1:0] are not zero, then a Data
Abort is generated and the MMU returns a Misaligned fault in the Fault Status Register.
4.3.12 Store word, little-endian
The 32-bit general-purpose register is stored to four bytes in memory where bits [7:0] of the
ARM register are transferred to the least-significant addressed byte in memory, as Figure 4-12
shows.
Figure 4-12 Store word, little-endian
If strict alignment fault checking is enabled and Address bits [1:0] are not zero, then a Data
Abort is generated and the MMU returns a Misaligned fault in the Fault Status Register.
4.3.13 Store word, big-endian
The 32-bit general-purpose register is stored to four bytes in memory where bits [31:24] of the
ARM register are transferred to the most-significant addressed byte in memory, as Figure 4-13
on page 4-12 shows.
B1
B0
Memory Register
31 23 15 7 0
Address
A[31:0]
70
B0 B1 B2 B3
B2
+1
lsbyte
msbyte
B3
+2
+3
Register
31 23 15 7 0
b3 b2 b1 b0
b1
b0
Memory
Address
A[31:0]
70
b2
+1
msbyte
lsbyte
b3
+2
+3
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