Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-24
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2.10 The program status registers
The processor contains one CPSR, and six SPSRs for exception handlers to use. The program
status registers:
• hold information about the most recently performed ALU operation
• control the enabling and disabling of interrupts
• set the processor operating mode.
Figure 2-10 shows the arrangement of bits in the status registers, and the sections from The
condition code flags to Reserved bits on page 2-29 inclusive describe it.
Figure 2-10 Program status register
Note
The bits that Figure 2-10 identifies as Do Not Modify (DNM), Read As Zero (RAZ), must not be
modified by software. These bits are:
• Readable, to enable the processor state to be preserved, for example, during process
context switches
• Writable, to enable the processor state to be restored. To maintain compatibility with
future ARM processors, and as good practice, you are strongly advised to use a
read-modify-write strategy when changing the CPSR.
2.10.1 The condition code flags
The N, Z, C, and V bits are the condition code flags. You can set them by arithmetic and logical
operations, and also by MSR and LDM instructions. The processor tests these flags to determine
whether to execute an instruction.
In ARM state, most instructions can execute conditionally on the state of the N, Z, C, and V bits.
The exceptions are:
•BKPT
•CDP2
•CPS
•LDC2
• MCR2
• MCRR2
• MRC2
• MRRC2
•PLD
N
31
30
29 28 27 26 25 24 23 20 19 16 15 10 9 8 7 6 5 4 0
Z C V Q
DNM
(RAZ)
J
DNM
(RAZ)
GE[3:0]
DNM
(RAZ)
E A I F T M[4:0]
Greater than
or equal to
Jazelle state bit
Sticky overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
Mode bits
Thumb state bit
FIQ disable
IRQ disable
Imprecise abort
disable bit
Data endianness bit
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