ARM ARM1176JZF-S - Figure 3-17 Memory Model Feature Register 0 Format; Table 3-20 Memory Model Feature Register 0 Bit Functions; Table 3-21 Results of Access to the Memory Model Feature Register 0

System Control Coprocessor
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c0, Memory Model Feature Register 0
The purpose of the Memory Model Feature Register 0 is to provide information about the
memory model, memory management, cache support, and TLB operations of the processor.
The Memory Model Feature Register 0 is:
•in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-17 shows the bit arrangement for Memory Model Feature Register 0.
Figure 3-17 Memory Model Feature Register 0 format
Table 3-20 lists how the bit values correspond with the Memory Model Feature Register 0
functions.
Table 3-21 lists the results of attempted access for each mode.
- - - - - -Reserved
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
-
Table 3-20 Memory Model Feature Register 0 bit functions
Bits Field name Function
[31:28] - Reserved. RAZ.
[27:24] - Indicates support for FCSE.
0x1 , ARM1176JZF-S processors support FCSE.
[23:20] - Indicates support for the ARMv6 Auxiliary Control Register.
0x1 , ARM1176JZF-S processors support the Auxiliary Control Register.
[19:16] - Indicates support for TCM and associated DMA.
0x3 , ARM1176JZF-S processors support ARMv6 TCM and DMA.
[15:12] - Indicates support for cache coherency with DMA agent, shared memory.
0x0 , ARM1176JZF-S processors do not support this model.
[11:8] - Indicates support for cache coherency support with CPU agent, shared memory.
0x0 , ARM1176JZF-S processors do not support this model.
[7:4] - Indicates support for Protected Memory System Architecture (PMSA).
0x0 , ARM1176JZF-S processors do not support PMSA
[3:0] - Indicates support for Virtual Memory System Architecture (VMSA).
0x3 , ARM1176JZF-S processors support:
• VMSA v7 remapping and access flag.
Table 3-21 Results of access to the Memory Model Feature Register 0
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Undefined exception Data Undefined exception Undefined exception