Cycle Timings and Interlock Behavior
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-24
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16.14 Synchronization instructions
This section describes the cycle timing behavior for the SWP, SWPB, LDREX, and STREX
instructions.
In all cases the base register, Rn, is an Early Reg, and requires an extra cycle of result latency to
provide its value. Table 16-21 lists the synchronization instructions cycle timing behavior.
CLREX instructions have cycle timing behavior as for load instructions. Because they have no
destination register, the result latency is not-applicable for such instructions.
Table 16-21 Synchronization Instructions cycle timing behavior
Instruction
Cycle
s
Memory Cycles Result latency
SWP Rd, <Rm>, [Rn]
22 3
SWPB Rd, <Rm>, [Rn]
22 3
LDREX <Rd>, [Rn]
11 3
STREX, <Rd>, <Rm>, [Rn]
11 3
LDREX{B,H,D} <Rd>, [Rn]
11 3
STREX{B,H,D} <Rd>, <Rm>, [Rn]
11 3
CLREX
11 X
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