System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-146
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At reset, the values in the System Validation Cache Size Mask Register are the correct values
for the implemented caches and TCMs.
Access to the System Validation Cache Size Mask Register in Secure User mode and in the
Non-secure world depends on the V bit, see c15, Secure User and Non-secure Access Validation
Control Register on page 3-132. Table 3-147 lists the results of attempted access for each mode.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
To use the System Validation Cache Size Mask Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c15
• CRm set to c14
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c15, c14, 0 ; Read System Validation Cache Size Mask Register
MCR p15, 0, <Rd>, c15, c14, 0 ; Write System Validation Cache Size Mask Register
[7] SBZ UNP/SBZ.
[6:4] DCache Specifies apparent size of Data Cache, as it appears to the processor. All other values are
reserved:
b011 = 4KB
b100 = 8KB
b101 = 16KB
b110 = 32KB
b111 = 64KB.
[3] SBZ UNP/SBZ.
[2:0] ICache Specifies apparent size of Instruction Cache, as it appears to the processor. All other values are
reserved:
b011 = 4KB
b100 = 8KB
b101 = 16KB
b110 = 32KB
b111 = 64KB.
Table 3-146 System Validation Cache Size Mask Register bit functions (continued)
Bits Field name Function
Table 3-147 Results of access to the System Validation Cache Size Mask Register
V
bit
Secure
Privileged
Non-secure Privileged User
Read Write Read Write Read Write
0 Data Data Undefined exception Undefined exception Undefined exception Undefined exception
1 Data Data Data Data Data Data
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