ARM ARM1176JZF-S User Manual

Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-30
ID012310 Non-Confidential, Unrestricted Access
1.9.1 Instruction progression
Figure 1-6 shows an LDR/STR operation that hits in the data cache.
Figure 1-6 Progression of an LDR/STR operation
Figure 1-7 shows the progression of an LDM/STM operation that completes by use of the
load/store pipeline. Other instructions can use the ALU pipeline at the same time as the
LDM/STM completes in the load/store pipeline.
Figure 1-7 Progression of an LDM/STM operation
Figure 1-8 on page 1-31 shows the progression of an LDR that misses. When the LDR is in the
HUM buffers, other instructions, including independent loads that hit in the cache, can run under
it.
MAC3
Not used
Sat
Saturation
Ex3
MAC2
Not used
ALU
Calculate
writeback
value
Ex2
MAC1
Not used
Sh
Shifter
operation
Ex1
1st fetch
stage
Fe1 Fe2 De Iss
2nd fetch
stage
Instruction
decode
Register
read and
instruction
issue
Not used
Common decode pipeline
Data
address
calculation
ADD DC1
First stage
of data
cache
access
DC2
Second
stage of
data cache
access
Writeback
from LSU
WBls
WBex
Base
register
writeback
ALU
pipeline
Load/store
pipeline
Hit under
miss
Multiply
pipeline
MAC3
Not used
Sat
Saturation
Ex3
MAC2
Not used
ALU
Calculate
writeback
value
Ex2
MAC1
Not used
Sh
Shifter
operation
Ex1
1st fetch
stage
Fe1 Fe2 De Iss
2nd fetch
stage
Instruction
decode
Register
read and
instruction
issue
Not used
unless a
miss
occurs
Common decode pipeline
WBex
Base
register
writeback
Data
address
calculation
ADD DC1
First stage
of data
cache
access
DC2
Second
stage of
data cache
access
Writeback
from LSU
WBls
ALU
pipeline
Load/store
pipeline
Hit under
miss
Multiply
pipeline

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English