ARM ARM1176JZF-S - Timing of the VIC Port; Figure 12-2 VIC Port Timing Example

Vectored Interrupt Controller Port
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12.3 Timing of the VIC port
Figure 12-2 shows a timing example of VIC port operation. In this example IRQC is received
followed by IRQB having a higher priority. The waveforms in Figure 12-2 show an
asynchronous relationship between CLKIN and HCLK, and the delays marked Sync cater for
the delay of the synchronizers. When this interface is used synchronously, these delays are
reduced to being a single cycle of the receiving clock.
Figure 12-2 VIC port timing example
Figure 12-2 illustrates the basic handshake mechanism that operates between the processor and
a PL192 VIC:
1. An IRQC interrupt request occurs causing the PL192 VIC to set the processor nIRQ
input.
2. The processor samples the nIRQ input LOW and initiates an interrupt entry sequence.
3. Another IRQB interrupt request of higher priority than IRQC occurs.
4. Between B3 and B4, the processor decides that the pending interrupt is an IRQ rather than
a FIQ and asserts the IRQACK signal.
5. At B4 the VIC samples IRQACK HIGH and starts generating IRQADDRV. The VIC
can still change IRQADDR to the IRQB vector address while IRQADDRV is LOW.
6. At B6 the VIC asserts IRQADDRV while IRQADDR is set to the IRQB vector address.
IRQADDR is held until the processor acknowledges it has sampled it, even if a higher
priority interrupt is received while the VIC is waiting.
7. Around B8 the processor samples the value of the IRQADDR input bus and deasserts
IRQACK.
8. When the VIC samples IRQACK LOW, it stacks the priority of the IRQB interrupt and
deasserts IRQADDRV. It also deasserts nIRQ if there are no higher priority interrupts
pending.
9. When the processor samples IRQADDRV LOW, it knows it can sample the nIRQ input
again. Therefore, if the VIC requires some time for deasserting nIRQ, it must ensure that
IRQADDRV stays HIGH until nIRQ has been deasserted.
Processor
clock
Peripheral port
HCLK
IRQC vector address IRQB vector address IRQADDR[31:2]
nIRQ
IRQACK
IRQADDRV
IRQC IRQB
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
Sync
Sync
Sync
Sync
Address sampled