ARM ARM1176JZF-S User Manual (English)

About the System Control Coprocessor134
Table 3-1 System Control Coprocessor Register Functions135
Figure 3-1 System Control and Configuration Registers137
Figure 3-2 MMU Control and Configuration Registers139
Figure 3-3 Cache Control and Configuration Registers140
Figure 3-4 TCM Control and Configuration Registers140
Figure 3-5 Cache Master Valid Registers141
Figure 3-6 DMA Control and Configuration Registers141
Figure 3-7 System Performance Monitor Registers142
Figure 3-8 System Validation Registers143
Figure 3-9 CP15 MRC and MCR Bit Pattern144
System Control Processor Registers145
- Table 3-2 Summary of CP15 Registers and Operations146
- Table 3-3 Summary of CP15 MCRR Operations151
- Figure 3-10 Main ID Register Format152
- Table 3-4 Main ID Register Bit Functions152
- Table 3-5 Results of Access to the Main ID Register152
- Figure 3-11 Cache Type Register Format153
- Table 3-6 Cache Type Register Bit Functions153
- Table 3-7 Results of Access to the Cache Type Register155
- Table 3-8 Example Cache Type Register Format155
- Figure 3-12 TCM Status Register Format156
- Table 3-9 TCM Status Register Bit Functions156
- Figure 3-13 TLB Type Register Format157
- Table 3-10 TLB Type Register Bit Functions157
- Table 3-11 Results of Access to the TLB Type Register157
- Figure 3-14 Processor Feature Register 0 Format158
- Table 3-12 Processor Feature Register 0 Bit Functions158
- Table 3-13 Results of Access to the Processor Feature Register 0159
- Figure 3-15 Processor Feature Register 1 Format160
- Table 3-14 Processor Feature Register 1 Bit Functions160
- Table 3-15 Results of Access to the Processor Feature Register 1160
- Figure 3-16 Debug Feature Register 0 Format161
- Table 3-16 Debug Feature Register 0 Bit Functions161
- Table 3-17 Results of Access to the Debug Feature Register 0161
- Table 3-18 Auxiliary Feature Register 0 Bit Functions162
- Table 3-19 Results of Access to the Auxiliary Feature Register 0162
- Figure 3-17 Memory Model Feature Register 0 Format163
- Table 3-20 Memory Model Feature Register 0 Bit Functions163
- Table 3-21 Results of Access to the Memory Model Feature Register 0163
- Figure 3-18 Memory Model Feature Register 1 Format164
- Table 3-22 Memory Model Feature Register 1 Bit Functions164
- Table 3-23 Results of Access to the Memory Model Feature Register 1165
- Figure 3-19 Memory Model Feature Register 2 Format166
- Table 3-24 Memory Model Feature Register 2 Bit Functions166
- Figure 3-20 Memory Model Feature Register 3 Format167
- Table 3-25 Results of Access to the Memory Model Feature Register 2167
- Table 3-26 Memory Model Feature Register 3 Bit Functions167
- Figure 3-21 Instruction Set Attributes Register 0 Format168
- Table 3-27 Results of Access to the Memory Model Feature Register 3168
- Table 3-28 Instruction Set Attributes Register 0 Bit Functions168
- Table 3-29 Results of Access to the Instruction Set Attributes Register 0169
- Figure 3-22 Instruction Set Attributes Register 1 Format170
- Table 3-30 Instruction Set Attributes Register 1 Bit Functions170
- Table 3-31 Results of Access to the Instruction Set Attributes Register 1170
- Figure 3-23 Instruction Set Attributes Register 2 Format171
- Table 3-32 Instruction Set Attributes Register 2 Bit Functions171
- Figure 3-24 Instruction Set Attributes Register 3 Format172
- Table 3-33 Results of Access to the Instruction Set Attributes Register 2172
- Table 3-34 Instruction Set Attributes Register 3 Bit Functions173
- Table 3-35 Results of Access to the Instruction Set Attributes Register 3173
- Figure 3-25 Instruction Set Attributes Register 4 Format174
- Table 3-36 Instruction Set Attributes Register 4 Bit Functions174
- Table 3-37 Results of Access to the Instruction Set Attributes Register 4175
- Table 3-38 Results of Access to the Instruction Set Attributes Register 5175
- Figure 3-26 Control Register Format176
- Figure177
- Table 3-39 Control Register Bit Functions177
- Figure179
- Table 3-40 Results of Access to the Control Register179
- Table 3-41 Resultant B Bit, U Bit, and EE Bit Values180
- Figure 3-27 Auxiliary Control Register Format181
- Table 3-42 Auxiliary Control Register Bit Functions181
- Table 3-43 Results of Access to the Auxiliary Control Register182
- Figure 3-28 Coprocessor Access Control Register Format183
- Table 3-44 Coprocessor Access Control Register Bit Functions183
- Table 3-45 Results of Access to the Coprocessor Access Control Register183
- Figure 3-29 Secure Configuration Register Format184
- Table 3-46 Secure Configuration Register Bit Functions184
- Table 3-47 Operation of the FW and FIQ Bits185
- Table 3-48 Operation of the AW and EA Bits185
- Figure 3-30 Secure Debug Enable Register Format186
- Table 3-49 Secure Debug Enable Register Bit Functions186
- Table 3-50 Results of Access to the Coprocessor Access Control Register187
- Figure 3-31 Non-Secure Access Control Register Format188
- Table 3-51 Non-Secure Access Control Register Bit Functions188
- Figure 3-32 Translation Table Base Register 0 Format189
- Table 3-52 Results of Access to the Auxiliary Control Register189
- Table 3-53 Translation Table Base Register 0 Bit Functions190
- Table 3-54 Results of Access to the Translation Table Base Register 0190
- Figure 3-33 Translation Table Base Register 1 Format191
- Table 3-55 Translation Table Base Register 1 Bit Functions191
- Table 3-56 Results of Access to the Translation Table Base Register 1192
- Figure 3-34 Translation Table Base Control Register Format193
- Table 3-57 Translation Table Base Control Register Bit Functions193
- Table 3-58 Results of Access to the Translation Table Base Control Register194
- Figure 3-35 Domain Access Control Register Format195
- Table 3-59 Domain Access Control Register Bit Functions195
- Table 3-60 Results of Access to the Domain Access Control Register195
- Figure 3-36 Data Fault Status Register Format196
- Table 3-61 Data Fault Status Register Bit Functions196
- Figure 3-37 Instruction Fault Status Register Format198
- Table 3-62 Results of Access to the Data Fault Status Register198
- Table 3-63 Instruction Fault Status Register Bit Functions199
- Table 3-64 Results of Access to the Instruction Fault Status Register199
- Table 3-65 Results of Access to the Fault Address Register200
- Table 3-66 Results of Access to the Instruction Fault Address Register201
- Figure 3-38 Cache Operations202
- Figure 3-39 Cache Operations with MCRR Instructions203
- Figure 3-40 C7 Format for Set and Index204
- Table 3-67 Functional Bits of C7 for Set and Index204
- Table 3-68 Cache Size and S Parameter Dependency204
- Figure 3-41 C7 Format for MVA205
- Figure 3-42 Format of C7 for VA205
- Table 3-69 Functional Bits of C7 for MVA205
- Table 3-70 Functional Bits of C7 for VA Format206
- Table 3-71 Cache Operations for Entire Cache206
- Table 3-72 Cache Operations for Single Lines207
- Table 3-73 Cache Operations for Address Ranges208
- Figure209
- Figure 3-43 Cache Dirty Status Register Format210
- Table 3-74 Cache Dirty Status Register Bit Functions210
- Figure 3-44 C7 Format for Flush Branch Target Entry Using MVA211
- Table 3-75 Cache Operations Flush Functions211
- Table 3-76 Flush Branch Target Entry Using MVA Bit Functions211
- Figure 3-45 PA Register Format for Successful Translation212
- Figure 3-46 PA Register Format for Aborted Translation212
- Table 3-77 PA Register for Successful Translation Bit Functions212
- Table 3-78 PA Register for Unsuccessful Translation Bit Functions213
- Table 3-79 Results of Access to the Data Synchronization Barrier Operation216
- Table 3-80 Results of Access to the Data Memory Barrier Operation217
- Table 3-81 Results of Access to the Wait for Interrupt Operation217
- Table 3-82 Results of Access to the TLB Operations Register218
- Figure 3-47 TLB Operations Register MVA and ASID Format219
- Figure 3-48 TLB Operations Register ASID Format219
- Figure 3-49 Instruction and Data Cache Lockdown Register Formats220
- Table 3-83 Instruction and Data Cache Lockdown Register Bit Functions220
- Table 3-84 Results of Access to the Instruction and Data Cache Lockdown Register220
- Figure 3-50 Data TCM Region Register Format222
- Table 3-85 Data TCM Region Register Bit Functions222
- Figure 3-51 Instruction TCM Region Register Format223
- Table 3-86 Results of Access to the Data TCM Region Register223
- Table 3-87 Instruction TCM Region Register Bit Functions224
- Figure 3-52 Data TCM Non-Secure Control Access Register Format225
- Table 3-88 Results of Access to the Instruction TCM Region Register225
- Table 3-89 Data TCM Non-Secure Control Access Register Bit Functions226
- Table 3-90 Effects of NS Items for Data TCM Operation226
- Figure 3-53 Instruction TCM Non-Secure Control Access Register Format227
- Table 3-91 Instruction TCM Non-Secure Control Access Register Bit Functions227
- Table 3-92 Effects of NS Items for Instruction TCM Operation227
- Figure 3-54 TCM Selection Register Format228
- Table 3-93 TCM Selection Register Bit Functions228
- Figure 3-55 Cache Behavior Override Register Format229
- Table 3-94 Results of Access to the TCM Selection Register229
- Table 3-95 Cache Behavior Override Register Bit Functions230
- Table 3-96 Results of Access to the Cache Behavior Override Register230
- Figure 3-56 TLB Lockdown Register Format232
- Table 3-97 TLB Lockdown Register Bit Functions232
- Table 3-98 Results of Access to the TLB Lockdown Register232
- Figure 3-57 Primary Region Remap Register Format234
- Table 3-99 Primary Region Remap Register Bit Functions234
- Figure 3-58 Normal Memory Remap Register Format235
- Table 3-100 Encoding for the Remapping of the Primary Memory Type235
- Table 3-101 Normal Memory Remap Register Bit Functions235
- Table 3-102 Remap Encoding for Inner or Outer Cacheable Attributes236
- Table 3-103 Results of Access to the Memory Region Remap Registers236
- Figure 3-59 DMA Identification and Status Registers Format238
- Table 3-104 DMA Identification and Status Register Bit Functions238
- Table 3-105 DMA Identification and Status Register Functions238
- Table 3-106 Results of Access to the DMA Identification and Status Registers239
- Figure 3-60 DMA User Accessibility Register Format240
- Table 3-107 DMA User Accessibility Register Bit Functions240
- Table 3-108 Results of Access to the DMA User Accessibility Register240
- Figure 3-61 DMA Channel Number Register Format241
- Table 3-109 DMA Channel Number Register Bit Functions241
- Table 3-110 Results of Access to the DMA Channel Number Register241
- Table 3-111 Results of Access to the DMA Enable Registers243
- Figure 3-62 DMA Control Register Format244
- Table 3-112 DMA Control Register Bit Functions244
- Table 3-113 Results of Access to the DMA Control Register245
- Table 3-114 Results of Access to the DMA Internal Start Address Register246
- Table 3-115 Results of Access to the DMA External Start Address Register247
- Table 3-116 Results of Access to the DMA Internal End Address Register248
- Figure 3-63 DMA Channel Status Register Format249
- Table 3-117 DMA Channel Status Register Bit Functions249
- Table 3-118 Results of Access to the DMA Channel Status Register251
- Figure 3-64 DMA Context ID Register Format252
- Table 3-119 DMA Context ID Register Bit Functions252
- Table 3-120 Results of Access to the DMA Context ID Register252
- Figure 3-65 Secure or Non-Secure Vector Base Address Register Format253
- Table 3-121 Secure or Non-Secure Vector Base Address Register Bit Functions253
- Figure 3-66 Monitor Vector Base Address Register Format254
- Table 3-122 Results of Access to the Secure or Non-Secure Vector Base Address Register254
- Table 3-123 Monitor Vector Base Address Register Bit Functions255
- Table 3-124 Results of Access to the Monitor Vector Base Address Register255
- Figure 3-67 Interrupt Status Register Format256
- Table 3-125 Interrupt Status Register Bit Functions256
- Table 3-126 Results of Access to the Interrupt Status Register256
- Figure 3-68 FCSE PID Register Format258
- Table 3-127 FCSE PID Register Bit Functions258
- Table 3-128 Results of Access to the FCSE PID Register258
- Figure 3-69 Address Mapping with the FCSE PID Register259
- Figure 3-70 Context ID Register Format260
- Table 3-129 Context ID Register Bit Functions260
- Table 3-130 Results of Access to the Context ID Register260
- Table 3-131 Results of Access to the Thread and Process ID Registers261
- Figure 3-71 Peripheral Port Memory Remap Register Format262
- Table 3-132 Peripheral Port Memory Remap Register Bit Functions263
- Table 3-133 Results of Access to the Peripheral Port Remap Register263
- Figure 3-72 Secure User and Non-Secure Access Validation Control Register Format264
- Table 3-134 Secure User and Non-Secure Access Validation Control Register Bit Functions264
- Figure 3-73 Performance Monitor Control Register Format265
- Table 3-136 Performance Monitor Control Register Bit Functions266
- Table 3-137 Performance Monitoring Events267
- Table 3-138 Results of Access to the Performance Monitor Control Register269
- Table 3-139 Results of Access to the Cycle Counter Register270
- Table 3-140 Results of Access to the Count Register 0271
- Table 3-141 Results of Access to the Count Register 1272
Table 3-142 System Validation Counter Register Operations272
Table 3-143 Results of Access to the System Validation Counter Register273
Figure 3-74 System Validation Counter Register Format for External Debug Request Counter273
Table 3-144 System Validation Operations Register Functions274
Table 3-145 Results of Access to the System Validation Operations Register275
Table 3-146 System Validation Cache Size Mask Register Bit Functions277
Figure 3-75 System Validation Cache Size Mask Register Format277
Table 3-147 Results of Access to the System Validation Cache Size Mask Register278
Table 3-148 TLB Lockdown Index Register Bit Functions281
Figure 3-76 TLB Lockdown Index Register Format281
Figure 3-77 TLB Lockdown VA Register Format281
Table 3-149 TLB Lockdown VA Register Bit Functions282
Table 3-150 TLB Lockdown PA Register Bit Functions282
Figure 3-78 TLB Lockdown PA Register Format282
Table 3-151 Access Permissions APX and AP Bit Fields Encoding283
Table 3-152 TLB Lockdown Attributes Register Bit Functions283
Figure 3-79 TLB Lockdown Attributes Register Format283
Table 3-153 Results of Access to the TLB Lockdown Access Registers284

Chapter 4 Unaligned and Mixed-Endian Data Access Support287

Chapter 5 Program Flow Prediction307

Chapter 6 Memory Management Unit319

Chapter 7 Level One Memory System373

Chapter 8 Level Two Interface389

Chapter 9 Clocking and Resets428

Chapter 10 Power Control438

Chapter 11 Coprocessor Interface445

Chapter 12 Vectored Interrupt Controller Port469

Chapter 13 Debug476

Chapter 14 Debug Test Access Port528

Chapter 15 Trace Interface Port569

Chapter 16 Cycle Timings and Interlock Behavior577

Chapter 17 AC Characteristics605

Chapter 18 Introduction to the VFP Coprocessor612

Chapter 19 The VFP Register File629

Chapter 20 VFP Programmer's Model642

Chapter 21 VFP Instruction Execution662

Chapter 22 VFP Exception Handling684

Appendix A Signal Descriptions711

Appendix B Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences727

ARM ARM1176JZF-S User Manual

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ARM ARM1176JZF-S Specifications

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Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English